According to the known art, “fatwire” structure is a wiring layout laid out with a metal line having thicker height and wider width, e.g., thickness and pitch of 2×, 4×, 6×, etc. of a thin wire, minimum ground rules dimensions. However, with regard to electromigration effects, reliability of fatwire structures with a larger pitch becomes worse than in a thin wire structure. This inconsistent reliability is due to the fatwire structure. In this regard, fatwire failure generally occurs at the top of the metal line, i.e., near the surface of the stripe, and/or at the bottom of the interlevel via. In the known structure, the bottom of the via may not fully contact the sidewall liner. Moreover, even when the via contacts the sidewall liner, the liner is too thin to sustain all the current density of the fatwire.
A conventional process for forming a dual damascene line is shown in FIGS. 1-4. In particular, a trench 12 is formed in a substrate 11 into which a metal, e.g., copper or aluminum, is provided, e.g., via electroplating, in order to form metal line Mx and at least one via Vx. Substrate 11 may be, e.g., SiO2, a low K organic material, a PCVD low dielectric material or other suitable material having a thickness of 400 to 2500 angstroms, metal line Mx may have a thickness in a range between 0.4-1.0 micron and a width of 0.2 to 1.0 micron, and via Vx may have a depth of 0.4 to 1.0 micron from the bottom of Mx and a diameter of 0.2 to 0.4 micron. Moreover, substrate 11 may optionally be covered by a hardmask layer 13, which can be, e.g., a PCVD oxide, SiCNH, SiC, Si3N4, or other suitable material. Moreover, the portion of hardmask 13 over trench 12 removed during the formation of trench 12 is filled with metal Mx. Further, metal line Mx is patterned by removing excess metal from the upper surface of substrate 11 or optional hardmask 13, e.g., through chemical mechanical polishing, to form a smooth upper surface.
In a next production step, a cap layer 14 is applied over the top of substrate 11/hardmask 13 and metal line Mx. Cap layer 14 can be, e.g., SiNx, SiCNH, or other suitable cap layer material for metal line Mx, and have a thickness of 200-1000 angstroms. A substrate or interlevel layer 15 is deposited onto cap layer 14. Interlayer 15, like substrate 11, can be, e.g., SiO2, a low K organic material, a PCVD low k-dielectric material or other suitable material having a thickness of 4000 (1×) to 24000 (6×). Optionally, a hardmask layer 16 can be deposited onto the surface of interlevel layer 15. Hardmask layer 16 can be, e.g., a PCVD oxide, SiCNH, or other suitable material with a thickness of 300-2000 angstroms.
In a next step in the conventional process, as shown in FIG. 2, a dual damascene trench 17 is formed in interlevel layer 15 and optional hardmask 16. Trench 17, which is formed by, e.g., lithography and etching, is composed of two portions: a first portion 18 extending to a depth of 0.6-2 micron from the surface of interlevel layer 15/hardmask 16 and a second portion 19 extending from first portion 18 down through cap layer 14 to contact metal line Mx.
As illustrated in FIG. 3, a liner 20 is deposited into trench 17 in order to form a barrier layer having a thickness of 50-500 angstroms. Liner 20 can be, e.g., Ta, TaN, W, Ti, TiN, or a combination of Ta, TaN, Ti, TiN, W or with other suitable material to act as a barrier layer for the metal to be deposited in liner 20. Moreover, liner 20 can be formed from one or more of the identified materials.
As noted above, and shown in FIG. 4, a metal, e.g., copper, is deposited in trench 17, and more particularly liner 20, in order to form metal line MQ in portion 18 of trench 17 and via VL in portion 19 of trench 17. Further, in accordance with the conventional process, wiring lines are patterned by removing excess metal from metal line MQ from the upper surface of substrate 15 or optional hardmask 16, e.g., through chemical mechanical polishing, to achieve a smooth upper surface with a metal stripe.